Research
13. Digital In-Memory Compute Engine for Improved Area Efficiency
Highlights: For next generation compute CPUs for AI workloads
12. Data Sorting using 6T SRAM Based In-Memory Computing
Team Members:
Rishabh Patil, IIT Indore
Ebrahim Rampurawala, IIT Indore
Highlights:
Performing data sorting using in-memory computing
Reduced latency
Improved area efficiency
11. Configurable Multi-Port Memory Architecture
Highlights:
Architecture to configure single port SRAM into multiport memory.
The architecture can configure the SRAM macro as either 1-port, 2-port, 3-port or 4-port memory.
The ports can be used for both read and write operations.
10. SHA-CNN: Scalable Hierarchical Aware CNN for Edge AI
Team Members:
Yuvnish Malhotra, BTech, IIT Indore
Highlights:
Modified CNN algorithm for hierarchical learning
Proposed algorithm performed SOTA performance with reduced computations
SHA-CNN is scalable for increased classes and levels
One step forward towards achieving human-level intelligence
9. Reconfigurable and Efficient In-Memory Computing using SRAM
Team Members:
Eshika Chittora, BTech, IIT Indore
Vishal Sharma, Post Doctoral, NTU Singapore
Highlights:
In-memory computing architecture for boolean conversions using 6T/10T SRAM
CAM string search operation was designed with low-latency
8. Memristor-Inspired Digital Logic Circuits Design
Team Member:
Megha Nawaria, MTech, IIT Indore
Shruti Sandip Ghodke, IIT Indore
Sanjay Kumar, PhD, IIT Indore
Highlights:
A novel Y2O3-based memristor model was proposed
Optimized digital logic and combinational circuits were designed with the proposed memristor model
7. Analog In-Memory Computing using RRAM
Team Members:
Radheshyam Sharma, MS, IIT Indore
Highlights:
A novel 1T2R memory bitcell is proposed for high-density memory applications
MAC operation was performed for neural network applications
6. ReCAM: RRAM Digital Content Addressable Memory
Team Members:
Radheshyam Sharma, MS, IIT Indore
Vishal Sharma, Intel
Highlights:
A novel 3T1R bitcell is proposed for high-density memory application
Content Addressable Memory (CAM) architecture for parallel string search operation was designed
Low latency and less energy performance were achieved
5. Hardware Accelerator for Deep Neural Network
Team Member:
Gopal Raut, PhD, IIT Indore
Neha Gupta, PhD, IIT Indore
Highlights:
Performance-centric, resources-efficient FC-DNN is presented
Reused activation functions by multiplexing the data-flow
Used Efficient memory addressing scheme to read/write weights and biases
Performance of DNN was evaluated on Virtex7 FPGA board
Improved area utilization and decreases in energy consumption
4. BitMAC: Bit-Serial Computation-based Efficient MAC for DNN Accelerator
Team Member:
Harsh Chhajed, MS, IIT Indore
Gopal Raut, PhD, IIT Indore
Highlights:
A semi-custom digital design approach for MAC unit is investigated for DNN applications
Bitcell architecture for 1-bit multiplication is proposed
Power-getting techniques was employed for power-saving
8-bit MAC unit is designed using proposed power-gated bitcell
3. Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators
Team Members:
Sudheer Vishwakarma, Intern, IIT Indore
Gopal Raut, PhD, IIT Indore
Highlights:
Introduced a reconfigurable activation function based on CORDIC and ROM
LeNet and VGG16 DNN model was deployed on the FPGA board and performance was evaluated
2. Soft Error hardened Voltage Bootstrapped Schmit Trigger for Reliable Circuits
Team Members:
Neha Gupta, PhD, IIT Indore
Gopal Raut, PhD, IIT Indore
Highlights:
Designed aging resilient and reliable voltage bootstrapped Schmitt trigger
Radiation tolerance methodology has been analyzed
Threshold voltage sensitivity has been analyzed with temperature variations
