Research

16. Digital In-Memory Compute Engine for Improved Area Efficiency 

Highlights: For next generation compute CPUs for AI workloads

15. Data Sorting using 6T SRAM Based In-Memory Computing

Team Members: 

• • • Rishabh Patil, BTech, IIT Indore

    • Ebrahim Rampurawala. IIT Indore

Highlights:

1.  Performing data sorting using in-memory computing

2.  Reduced latency

3. Improved area efficiency

14. Multi-Port Memory Architecture for Parallel Communication

Highlights:

1.  Architecture to configure single port SRAM into multiport memory.

2.  The architecture can configure the SRAM macro as either 1-port, 2-port, 3-port or 4-port memory.

3.  The ports can be used for both read and write operations.

13. SHA-CNN: Scalable Hierarchical Aware CNN for Edge AI

Team Members: 

• • • Yuvnish Malhotra, BTech, IIT Indore (Currently with Rakuten)

Highlights:

1. Modified CNN algorithm for hierarchical learning

2. Proposed algorithm performed SOTA performance with reduced computations

3. SHA-CNN is scalable for increased classes and levels

4. One step forward towards achieving human-level intelligence

12. In-Memory Computing with 6T SRAM for Multi-Operator Logic Design

Team Members:

• • • Eshika Chittora, BTech, IIT Indore (Currently with NVIDIA)

    • Vishal Sharma, Post Doctoral, NTU Singapore (Currently with Intel)

Highlights:

1. Designed in-memory computing architecture for boolean conversions

2. Complete reconfigurable memory architecture was designed and evaluated

11. Reconfigurable and Efficient Digital In-Memory Computing using novel 10T SRAM

Team Members: 

• • • Eshika Chittora, BTech, IIT Indore (Currently with NVIDIA)

    • Vishal Sharma, Post Doctoral, NTU Singapore (Currently with Intel)

Highlights:

1. A novel 10T SRAM bitcell was proposed for BNN

2. Low latency and high SNM was achieved

3. In-memory computing architecture for boolean computation was designed

4. CAM string search operation was designed with low-latency

10. Memristor-Inspired Digital Logic Circuits Design

Team Member: 

• • • Megha Nawaria, MTech, IIT Indore (Currently with Qualcomm)

    • Shruti Sandip Ghodke, IIT Indore (Currently with Synopsys)

    • Sanjay Kumar, PhD, IIT Indore (Currently with University of Edinburgh)

Highlights:

1. A novel Y2O3-based memristor model was proposed

2. Optimized digital logic and combinational circuits were designed with the proposed memristor model

9. Analog In-Memory Computing using RRAM

Team Members: 

• • • Radheshyam Sharma, MS, IIT Indore (Currently with GlobalFoundries)

Highlights:

1. A novel 1T2R memory bitcell is proposed for high-density memory applications

2. MAC operation was performed for neural network applications

8. ReCAM: RRAM Digital Content Addressable Memory

Team Members: 

• • Radheshyam Sharma, MS, IIT Indore (Currently with GlobalFoundries)

  • Vishal Sharma, Intel Technology

Highlights:

1. A novel 3T1R bitcell is proposed for high-density memory application

2. Content Addressable Memory (CAM) architecture for parallel string search operation was designed

3. Low latency and less energy performance were achieved

7. Hardware Accelerator for Deep Neural Network

Team Member: 

• • • Gopal Raut, PhD, IIT Indore (Currently with CDAC)

    • Neha Gupta, PhD, IIT Indore (Currently with Cadence)

Highlights:

1. Performance-centric, resources-efficient FC-DNN is presented 

2. Reused activation functions by multiplexing the data-flow

3. Used Efficient memory addressing scheme to read/write weights and biases 

4. Performance of DNN was evaluated on Virtex7 FPGA board

5. Improved area utilization and decreases in energy consumption

6. BitMAC: Bit-Serial Computation-based Efficient MAC for DNN Accelerator

Team Member: 

• • • Harsh Chhajed, MS, IIT Indore (Currently with IBM)

    • Gopal Raut, PhD, IIT Indore (Currently with CDAC)

Highlights:

1. A semi-custom digital design approach for MAC unit is investigated for DNN applications

2. Bitcell architecture for 1-bit multiplication is proposed

3. Power-getting techniques was employed for power-saving

4. 8-bit MAC unit is designed using proposed power-gated bitcell

5. Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators

Team Members: 

• • • Sudheer Vishwakarma, Intern, IIT Indore (Currently with Oulu University, Finland)

    • Gopal Raut, PhD, IIT Indore (Currently with CDAC Bangalore)

Highlights:

1. Introduced a reconfigurable activation function based on CORDIC and ROM

2. LeNet and VGG16 DNN model was deployed on the FPGA board and performance was evaluated

4. SRAM Memory Compiler

Team Members: 

• • • Eshika Bhosale, BTech, IIT Indore (Currently with Rakuten)

Highlights:

1. OpenRAM memory compiler was customized for SCL 180nm technology

2. A 1KB memory array was designed with peripheral circuitry

3. Power on Initialization of SRAM Cell for FPGA

Team Members: 

• • Radheshyam Sharma, MS, IIT Indore (Currently with GlobalFoundries)

  • Govindu Sathvik Reddy, BTech, IIT Indore (Currently with NVIDIA)

Highlights:

1. Self set/reset methodology was proposed for 6T SRAM memory

2. The proposed method doesn't require any additional Scircuitry for set/reset

3. SNM and delay performance was evaluated as compared with SOTA

4. Array-level performance was evaluated for energy efficiency

2. Soft Error hardened Voltage Bootstrapped Schmit Trigger for Reliable Circuits

Team Members: 

• • • Neha Gupta, PhD, IIT Indore (Currently with Cadence)

    • Gopal Raut, PhD, IIT Indore (Currently with CDAC)

Highlights:

1. Designed aging resilient and reliable voltage bootstrapped Schmitt trigger

2. Radiation tolerance methodology has been analyzed 

3. Threshold voltage sensitivity has been analyzed with temperature variations

1. Voltage Controlled Oscillator using Injection Locking Technique

Highlights:

1. Designed ring and LC-based VCO using injection locking

2. Performance of phase noise, tuning range voltage swing and power dissipation were evaluated